1. Field of the Invention
The present invention relates to a method for compensating for clock signal difference between a switch and peripheral devices and the associated apparatus. More particularly, the present invention relates to a method for compensating for clock signal difference between a switch for an Ethernet and peripheral devices.
2. Description of the Related Art
As the internet continues to be developed, requirements of accuracy and transmission speed for transmitting data through the internet increase. Particularly, in a switch for an Ethernet system, high accuracy and transmission speed is also required.
FIG. 1 is a block diagram illustrating connections between a conventional switch and a test device. For understanding the quality of a conventional switch 100, a test device 102 is used to perform a wire-speed forwarding test to the switch 100. The test device 102 periodically outputs a number of packets to the switch 100, and then the switch 100 redirects these packets to corresponding ports according to the headers of the packets. As shown in FIG. 1, the packets out of the medium access control (MAC) unit 103 of the test device 102 is transmitted to a receive medium access control (RMAC) unit 104 of the switch 100. After being processed by the RMAC unit 104, the received packets are transmitted to an input control unit 106. The input control unit 106 is used for subsequent processing, and the processed packets are then temporarily stored in a memory 108. If the RMAC unit 104 detects errors in the received packets, it alerts the input control unit 106 to stop subsequent processing.
In addition, an output control unit 110 reads packets stored in the memory 108 and then alerts a transmit medium access control (TMAC) unit 112 to transmit the packets. The RMAC unit 104 and the TMAC unit 112 as a whole are in general called a MAC unit 114 of the switch 100.
The inter-packet gap (IPG) between two adjacent packets is at least 96 bit time in regard to the specification of the Ethernet. Furthermore, the frequency of the MAC unit 114 of the switch must be the same as that of the MAC unit 103 of the test device 102. For example, for a 100 M bps (bit per second) Ethernet system, each bit time is equal to 10 ns (10−9 sec), and then a 50 MHz clock signal is used for both MAC units 103 and 114, wherein two bits are transmitted every RMII (Reduced Media Independent Interface) clock cycle which is essentially equal to two bit time.
First, assume that the MAC unit 103 of the test device 102 operates at a first clock domain with a frequency FRQ1 and the MAC unit 114 of the switch operates at a second clock domain with a frequency FRQ2. FIG. 2A is a schematic diagram for illustrating input and output packets of the switch when the frequencies of the MAC unit of the test device and the MAC unit of the switch are the same. For a 100 M bps Ethernet system, assume that both of the frequencies FRQ1 and FRQ2 are equal to 50 MHz and 96 bit time is equal to 48 clock cycles. After the MAC unit 103 of the test device 102 has transmitted the packet P1, packets P2, P3, and P4 are then respectively and subsequently transmitted every 48 clock cycles (the first clock domain). On the other hand, the packets P1, P2, P3, and P4 are received by the MAC unit 114 of the switch 100 and temporarily stored in a buffer (not shown) therein. Then, the packets P1, P2, P3, and P4 are respectively and subsequently transmitted to the memory 108 every 48 clock cycles (the second clock domain). As the input (a) signal shown in FIG. 2A, the IPGs of the adjacent packets of the packets P1, P2, P3 and P4 are 96 bit time.
Each IPG must be larger than or equal to 96 bit time according to the Ethernet specification and therefore, after the TMAC unit 112 reads the packet P1 from the memory 108, the packets P2, P3, and P4 are read from the memory 108 every 48 clock cycles (the second clock domain). As can be learned from output signal (a) shown in FIG. 2A, which is outputted from the memory 108 to the TMAC unit 112 in FIG. 1, each IPG of the adjacent packets of the packets P1, P2, P3 and P4 is equal to 96 bit time. Similarly, when the switch 100 transmits the packets P1, P2, P3, and P4, each IPG of the packets P1, P2, P3, and P4 is also equal to 96 bit time (the second clock domain). Because the frequency FRQ1 of the first clock domain is equal to the frequency FRQ2 of the second clock domain, each of the IPGs among the packets P1, P2, P3, and P4 transmitted from the RMAC unit 104 to the memory 108 and each of the IPGs among the packets P1, P2, P3, and P4 transmitted from the memory 108 to the TMAC unit 112 are equal. Therefore, the packets are not jammed in the memory 108, and the transmission of the packets is successful.
FIG. 2B is a schematic diagram for illustrating input and output packets of the switch when the frequencies of the MAC unit of the test device and the MAC unit of the switch are not equal. According to the Ethernet specification, a frequency tolerance between −100 ppm to +100 ppm (1 ppm=10−6) is allowed. As an example, when a maximum frequency tolerance of 200 ppm occurs for an Ethernet system having a frequency of 100 MHz between the MAC unit 114 of the switch 100 and the MAC unit 103 of the test device 102, the frequencies FRQ1 and FRQ2 can be respectively (1+100 ppm)×50 MHz and (1−100 ppm)×50 MHz.
TABLE I shows the IPG probability for different packet sizes when the difference between the frequencies FRQ1 and FRQ2 is 200 ppm.
TABLE IPacket size (byte)6451210241518Byte accumulation0.13440.85121.67042.4608Probability (IPG = 96)0.93280.57440.16480Probability (IPG = 94)0.06720.42560.83520.7696Probability (IPG = 92)0000.2304Packet number for14.88102.349621.19732IPG = 94Packet number for2.17014IPG = 92
Take the packet size of 64 byte as an example. After the MAC unit 103 of the test device 102 transmits the packet P1, the packets P2, P3, and P4 are consecutively transmitted every 48 clock cycles (the first clock domain). After the MAC 114 of the switch 100 receives the packets P1, P2, P3, and P4, they are temporarily stored in a buffer (not shown) of the RMAC unit 104 and then respectively transmitted to the memory 108.
As shown in TABLE I, because frequencies FRQ1 and FRQ2 are different, the speed of transmitting the packets from the RMAC unit 104 to the memory 108 is lower than that of transmitting the packets from the test device 102 to the RMAC unit 104. Accordingly, the packets accumulate in the buffer of the RMAC unit 104. For example, from TABLE I, 0.1344 bit accumulate in the buffer of the RMAC unit 104 for transmitting a 64-byte packet. Therefore, two bits are accumulated in the buffer of the RMAC unit 104 after 14.8810 64-byte packets are transmitted.
In order to prevent the received packets from accumulating in the buffer of the RMAC 104, the IPG has to be reduced by two bit time after each 14.8810 64-byte packets are transmitted. As shown in FIG. 2B, the input signal (b) transmitted from RMAC unit 104 to the memory 108, the IPG between the packets P2 and P3 is 94 bit time. Namely, the RMAC unit 104 reduces the IPG between the packets P2 and P3 to 94 bit time and then transmits them to the memory 108. As shown in TABLE I, the probability that the RMAC unit 104 reduces the IPG between the packets to 94 bit time and then transmits them to the memory 108 is 0.0672.
Since, according to the Ethernet specification, each IPG must be larger than or equal to 96 bit time, after the TMAC unit 112 read the packet P1 from the memory 108, the packets P2, P3, and P4 are read from the memory 108 every 48 clock cycles (the second clock domain). As can be learned from output signal (b) as shown in FIG. 2A, which is outputted from the memory 108 to the TMAC unit 112 in FIG. 1, each IPG of the adjacent packets of the packets P1, P2, P3, and P4 outputted from the memory 108 is equal to 96 bit time. Similarly, when the switch 100 transmits the packets P1, P2, P3, and P4, in which the corresponding IPGs are also equal to 96 bit time (the second clock domain).
However, because the frequency FRQ1 of the first clock domain and the frequency FRQ2 of the second clock domain are not equal, the sum of all IPGs of the adjacent packets of the packets P1, P2, P3, and P4 from the RMAC unit 104 to the memory 108 is less than that of all IPGs of the packets P1, P2, P3 and P4 from the memory 108 to the TMAC unit 112. Namely, the speed for storing the packet into the memory 108 is larger than that for reading the packet from the memory 108. An overflow is occurred in the memory 108 of the switch 100. Therefore, the subsequent packet cannot be continuously transmitted to the memory 108 so as to lose data. To avert this, a flow control unit 116 of the switch 100 has to be triggered to delay the data transmission so as to reduce transmission rate for the network.
Another example of switch is described in U.S. Pat. No. 5,719,862 to Raymond K. Lee, et al. In this technique, dynamic de-skewing is performed for each packet in a switch and each data packet transmitted through the switch is compensated for skew by measuring the skew of the start flag transmitted with the data packet.